Embodiments of the present disclosure relate to a semiconductor device, and more particularly to a semiconductor device configured to maximize driving ability of a plurality of drivers installed in a given region when the plurality of drivers is arranged in an array.
Generally, it is very difficult to guarantee sufficient space needed to construct a layout of constituent elements and lines in highly integrated semiconductor devices such as DRAMs. Accordingly, it is very important to properly arrange constituent elements and lines within a restricted space in terms of a layout aspect.
FIG. 1 is a plan view illustrating conventional arrayed drivers arranged in parallel to one another according to the related art. In more detail, FIG. 1 illustrates a multi-finger arrangement structure in which each driver (DRV) includes two gate fingers.
When conventional drivers are arranged in an array, two gates for each driver are arranged to share a source as shown in FIG. 1, such that the entire arrangement region can be reduced in size. In this case, in order to arrange such gates according to the restricted rule on the condition that the size of the arrangement region is limited to a predetermined size, there is a need to guarantee a sufficiently large space between gates as compared to the length of the gates.
As a result, it is difficult to adjust a Critical Dimension (CD) of the gates, and it is also impossible to properly adjust a size of a space between a contact (M0C) configured to interconnect a metal line and an active region and each gate, resulting in deterioration of transistor characteristics.
In addition, since each driver includes two gate fingers in the arrangement structure shown in FIG. 1, a transistor width capable of being realized within a predetermined region is reduced such that a driving ability of the transistor is deteriorated. In addition, the chip region is increased in size, resulting in a reduction of the number of net dies.
In addition, since all drivers for use in the arrangement structure shown in FIG. 1 are designed to share a source, all the drivers must be formed in only one active region. As a result, the dishing and erosion amount unavoidably increases during ISO (isolation) Chemical Mechanical Polishing (CMP), such that modification of an ISO layer occurs, resulting in deterioration of circuit throughput.